Renesas Electronics /R7FA6M4AF /GPT_OPS /OPSCR

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Interpret as OPSCR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (UF)UF 0 (VF)VF 0 (WF)WF 0 (U)U0 (V)V0 (W)W0 (0)EN 0 (0)FB 0 (0)P0 (0)N0 (0)INV 0 (0)RV 0 (0)ALIGN 0GRP0 (0)GODF 0 (0)NFEN 0 (00)NFCS

NFEN=0, NFCS=00, GODF=0, FB=0, RV=0, INV=0, P=0, EN=0, N=0, ALIGN=0

Description

Output Phase Switching Control Register

Fields

UF
VF
WF
U

Input U-Phase Monitor

V

Input V-Phase Monitor

W

Input W-Phase Monitor

EN

Output Phase Enable

0 (0): Do not output (Hi-Z external pin)

1 (1): Output

FB

External Feedback Signal Enable

0 (0): Select the external input

1 (1): Select the soft setting (OPSCR.UF, VF, WF)

P

Positive-Phase Output (P) Control

0 (0): Level signal output

1 (1): PWM signal output

N

Negative-Phase Output (N) Control

0 (0): Level signal output

1 (1): PWM signal output

INV

Output Phase Invert Control

0 (0): Positive logic (active-high) output

1 (1): Negative logic (active-low) output

RV

Output Phase Rotation Direction Reversal Control

0 (0): Positive rotation

1 (1): Reverse rotation

ALIGN

Input Phase Alignment

0 (0): Input phase aligned to PCLKD

1 (1): Input phase aligned to the falling edge of PWM

GRP

Output Disabled Source Selection

GODF

Group Output Disable Function

0 (0): This bit function is ignored

1 (1): Group disable clears the OPSCR.EN bit

NFEN

External Input Noise Filter Enable

0 (0): Do not use a noise filter on the external input

1 (1): Use a noise filter on the external input

NFCS

External Input Noise Filter Clock Selection

0 (00): PCLKD/1

1 (01): PCLKD/4

2 (10): PCLKD/16

3 (11): PCLKD/64

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